Macros for atomic 'OR' and 'AND' operations introduced.
Compiler built-ins used, where possible. Necessary configure checks added.
New macros:
nxt_atomic_or_fetch(ptr, val)
nxt_atomic_and_fetch(ptr, val)
Syntax and behaviour is similar to __sync_or_and_fetch and __sync_and_and_fetch
GCC build-ins.
This commit is contained in:
@@ -21,6 +21,10 @@ nxt_feature_test="int main() {
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return 1;
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return 1;
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if (n != 5)
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if (n != 5)
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return 1;
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return 1;
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if (__sync_or_and_fetch(&n, 2) != 7)
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return 1;
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if (__sync_and_and_fetch(&n, 5) != 5)
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return 1;
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__sync_lock_release(&n);
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__sync_lock_release(&n);
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if (n != 0)
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if (n != 0)
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return 1;
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return 1;
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@@ -51,6 +55,10 @@ if [ $nxt_found = no ]; then
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return 1;
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return 1;
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if (n != 5)
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if (n != 5)
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return 1;
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return 1;
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if (atomic_or_ulong_nv(&n, 2) != 7)
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return 1;
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if (atomic_and_ulong_nv(&n, 5) != 5)
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return 1;
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return 0;
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return 0;
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}"
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}"
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. auto/feature
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. auto/feature
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@@ -51,6 +51,14 @@ nxt_atomic_release(lock) \
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__sync_lock_release(lock)
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__sync_lock_release(lock)
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#define nxt_atomic_or_fetch(ptr, val) \
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__sync_or_and_fetch(ptr, val)
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#define nxt_atomic_and_fetch(ptr, val) \
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__sync_and_and_fetch(ptr, val)
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#if (__i386__ || __i386 || __amd64__ || __amd64)
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#if (__i386__ || __i386 || __amd64__ || __amd64)
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#define \
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#define \
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nxt_cpu_pause() \
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nxt_cpu_pause() \
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@@ -85,6 +93,15 @@ nxt_atomic_xchg(lock, set) \
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nxt_atomic_fetch_add(value, add) \
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nxt_atomic_fetch_add(value, add) \
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(atomic_add_long_nv(value, add) - add)
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(atomic_add_long_nv(value, add) - add)
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#define nxt_atomic_or_fetch(ptr, val) \
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atomic_or_ulong_nv(ptr, val)
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#define nxt_atomic_and_fetch(ptr, val) \
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atomic_and_ulong_nv(ptr, val)
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/*
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/*
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* Solaris uses SPARC Total Store Order model. In this model:
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* Solaris uses SPARC Total Store Order model. In this model:
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* 1) Each atomic load-store instruction behaves as if it were followed by
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* 1) Each atomic load-store instruction behaves as if it were followed by
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